dangernoodle-io / TaipanMiner / 24811641617

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fix: switch BM1370 UART baud to 1 Mbps after PLL ramp, not before (#151)

the ASIC derives its UART clock divider from the PLL. switching the ESP
link to 1 Mbps while the PLL is still stepping up from 6.25 MHz means
the ASIC's TX eye is malformed until the PLL settles at target. symptom
is uart_read_bytes driver error spam above some frequency ceiling that
varies with target.

ESP-Miner runs the ramp entirely at 115200 and only promotes to 1 Mbps
after init returns; doing the same here. refs TA-190.

Co-authored-by: Claude Opus 4.7 <noreply@anthropic.com>

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