24303773356
92%

Ran 12 Apr 2026 09:55AM UTC

Jobs 1

Files 102

Run time 1min

Badge

Committed 12 Apr 2026 09:42AM UTC coverage: 92.333% (-0.003%) from 92.336%

Build Type

push

github

Committed by

Commit Message

Fix crash with Verilog wire initialiser in generate block

Test case from #1486

Coverage Stats

43 of 43 new or added lines in 1 file covered. (100.0%)

45 existing lines in 4 files now uncovered.

76577 of 82936 relevant lines covered (92.33%)

608912.49 hits per line

Lines	Coverage	∆	File
38	78.13	4.34%	src/vhdl/vhdl-lower.c
5	97.64	0.0%	src/mir/mir-optim.c
1	88.3	-0.14%	src/jit/jit-interp.c
1	97.78	0.12%	src/mir/mir-node.c

ID	Job ID	Ran	Files	Coverage
1	24303773356.1	12 Apr 2026 09:55AM UTC	102	92.33	GitHub Action Run