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nickg / nvc / 24234165755
92%
master: 92%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 10 Apr 2026 08:45AM UTC
Jobs 1
Files 101
Run time 1min
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10 Apr 2026 08:33AM UTC coverage: 92.339% (+0.001%) from 92.338%
24234165755

Pull #1486

github

web-flow
Merge cd5a56bb0 into e00449bb3
Pull Request #1486: Verilog: fix wire initialiser scoping inside generate blocks

27 of 27 new or added lines in 1 file covered. (100.0%)

76347 of 82681 relevant lines covered (92.34%)

617687.63 hits per line

Jobs
ID Job ID Ran Files Coverage
1 24234165755.1 10 Apr 2026 08:45AM UTC 101
92.34
GitHub Action Run
Source Files on build 24234165755
  • Tree
  • List 101
  • Changed 1
  • Source Changed 0
  • Coverage Changed 1
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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  • Pull Request #1486
  • PR Base - master (#24179884388)
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