nickg / nvc / 24179884388

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 Verilog: support constant user functions and if-generate elaboration (#1483)

Verilog: support constant user functions and if-generate elaboration

Three related fixes for Verilog generate block elaboration:

1. vlog-sem.c: Mark user function calls as constant expressions
   (TM_CONST) when all arguments are constant, per IEEE 1800-2023
   section 11.2.1.  This allows constant functions to be used in
   contexts that require constant expressions such as localparam
   initializers and part-select bounds.

2. elab.c: Add JIT-based evaluation of Verilog if-generate conditions
   at elaboration time, mirroring the existing for-generate mechanism.
   Previously if-generate blocks that survived simplification (e.g.
   conditions depending on constant function results) would error with
   "if-generate construct could not be evaluated at elaboration time".

3. vlog-lower.c: Lower local variable declarations in named begin/end
   blocks inside functions and tasks.  Variables declared inside a
   named block (e.g. "begin : name integer i; ...") were not being
   created as MIR variables, causing a fatal "missing variable" error
   when the function was called.

Co-authored-by: Rafał Hibner <rafal.hibner@secom.com.pl>

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23 of 24 new or added lines in 3 files covered. (95.83%)

2 existing lines in 1 file now uncovered.

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