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nickg / nvc / 23186320325
92%

Build:
DEFAULT BRANCH: master
Ran 17 Mar 2026 09:10AM UTC
Jobs 1
Files 102
Run time 1min
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17 Mar 2026 09:00AM UTC coverage: 92.484% (+0.003%) from 92.481%
23186320325

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github

nickg
Correct size and sign extension rules for Verilog case statement

91 of 95 new or added lines in 4 files covered. (95.79%)

77868 of 84196 relevant lines covered (92.48%)

443248.57 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
93.34
0.0% src/jit/jit-core.c
3
97.8
-0.08% src/jit/jit-irgen.c
Jobs
ID Job ID Ran Files Coverage
1 23186320325.1 17 Mar 2026 09:10AM UTC 102
92.48
GitHub Action Run
Source Files on build 23186320325
  • Tree
  • List 102
  • Changed 3
  • Source Changed 0
  • Coverage Changed 3
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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