nickg / nvc / 20081005080
93%

DEFAULT BRANCH: master
Ran
Jobs 1
Files 100
Run time 1min
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Rst
coverage: 92.605% (-0.003%) from 92.608%
20081005080

push

github

nickg 
Code generation for Verilog exponentiation operator

28 of 32 new or added lines in 3 files covered. (87.5%)

1 existing line in 1 file now uncovered.

75398 of 81419 relevant lines covered (92.6%)

416326.9 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
4
94.39
 -0.36% src/jit/jit-exits.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
94.39
 -0.36% src/jit/jit-exits.c
Jobs
ID Job ID Ran Files Coverage
1 20081005080.1 100
92.6
 GitHub Action Run
Source Files on build 20081005080