nickg / nvc / 17516785922
93%
master: 93%

LAST BUILD BRANCH: random-initialization
DEFAULT BRANCH: master
Ran
Jobs 1
Files 99
Run time 1min
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Rst
coverage: 92.653% (+0.005%) from 92.648%
17516785922

push

github

nickg 
Basic code generation for System Verilog enums

95 of 99 new or added lines in 6 files covered. (95.96%)

175 existing lines in 4 files now uncovered.

73309 of 79122 relevant lines covered (92.65%)

576747.53 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
2
96.28
 -0.11% src/vlog/vlog-lower.c
2
75.45
 -0.25% src/vlog/vlog-trans.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
96.28
 -0.11% src/vlog/vlog-lower.c
5
94.63
 0.32% src/vlog/vlog-sem.c
65
94.86
 -0.12% src/elab.c
104
96.43
 0.02% src/vlog/vlog-parse.c
Jobs
ID Job ID Ran Files Coverage
1 17516785922.1 99
92.65
 GitHub Action Run
Source Files on build 17516785922