nickg / nvc / 17513768111
93%
master: 93%

LAST BUILD BRANCH: random-initialization
DEFAULT BRANCH: master
Ran
Jobs 1
Files 99
Run time 1min
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Rst
coverage: 92.648% (+0.01%) from 92.635%
17513768111

push

github

nickg 
Handle more Verilog operator assignments

29 of 32 new or added lines in 5 files covered. (90.63%)

73204 of 79013 relevant lines covered (92.65%)

584934.77 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
3
45.45
 1.17% src/vpi/vpi-util.c
Jobs
ID Job ID Ran Files Coverage
1 17513768111.1 99
92.65
 GitHub Action Run
Source Files on build 17513768111