nickg / nvc / 17359855326
93%
master: 93%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 99
Run time 3min
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst
coverage: 92.624% (-0.02%) from 92.64%
17359855326

push

github

nickg 
Short-circuiting for Verilog && and || operators

79 of 82 new or added lines in 5 files covered. (96.34%)

70 existing lines in 3 files now uncovered.

72919 of 78726 relevant lines covered (92.62%)

574206.0 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
96.4
 -0.01% src/vlog/vlog-parse.c
2
96.38
 -0.04% src/vlog/vlog-lower.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
96.38
 -0.04% src/vlog/vlog-lower.c
24
87.61
 0.0% src/scan.c
45
93.6
 -2.15% src/lexer.l
Jobs
ID Job ID Ran Files Coverage
1 17359855326.1 99
92.62
 GitHub Action Run
Source Files on build 17359855326