nickg / nvc / 17342814260
93%
master: 93%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 98
Run time 1min
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Rst
coverage: 92.621% (+0.03%) from 92.59%
17342814260

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github

nickg 
Elaboration for Verilog for-generate blocks

167 of 168 new or added lines in 8 files covered. (99.4%)

134 existing lines in 8 files now uncovered.

72750 of 78546 relevant lines covered (92.62%)

562031.35 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
83.3
 0.18% src/vpi/vpi-model.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
88.95
 -0.14% src/jit/jit-interp.c
1
72.22
 0.0% src/vlog/vlog-trans.c
5
93.75
 -0.17% src/vlog/vlog-sem.c
11
82.11
 0.0% src/vlog/vlog-util.c
14
96.31
 0.06% src/vlog/vlog-lower.c
14
88.76
 1.05% src/vlog/vlog-udp.c
27
94.95
 0.08% src/elab.c
61
90.22
 0.01% src/vlog/vlog-dump.c
Jobs
ID Job ID Ran Files Coverage
1 17342814260.1 98
92.62
 GitHub Action Run
Source Files on build 17342814260