• Home
  • Features
  • Pricing
  • Docs
  • Announcements
  • Sign In

nickg / nvc / 17342814260
93%
master: 93%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 30 Aug 2025 10:56AM UTC
Jobs 1
Files 98
Run time 1min
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst

30 Aug 2025 10:41AM UTC coverage: 92.621% (+0.03%) from 92.59%
17342814260

push

github

nickg
Elaboration for Verilog for-generate blocks

167 of 168 new or added lines in 8 files covered. (99.4%)

134 existing lines in 8 files now uncovered.

72750 of 78546 relevant lines covered (92.62%)

562031.35 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
83.3
0.18% src/vpi/vpi-model.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
88.95
-0.14% src/jit/jit-interp.c
1
72.22
0.0% src/vlog/vlog-trans.c
5
93.75
-0.17% src/vlog/vlog-sem.c
11
82.11
0.0% src/vlog/vlog-util.c
14
96.31
0.06% src/vlog/vlog-lower.c
14
88.76
1.05% src/vlog/vlog-udp.c
27
94.95
0.08% src/elab.c
61
90.22
0.01% src/vlog/vlog-dump.c
Jobs
ID Job ID Ran Files Coverage
1 17342814260.1 30 Aug 2025 10:56AM UTC 98
92.62
GitHub Action Run
Source Files on build 17342814260
  • Tree
  • List 98
  • Changed 16
  • Source Changed 0
  • Coverage Changed 16
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
  • Back to Repo
  • b897f732 on github
  • Prev Build on test (#17331952033)
  • Next Build on test (#17346274433)
STATUS · Troubleshooting · Open an Issue · Sales · Support · CAREERS · ENTERPRISE · START FREE · SCHEDULE DEMO
ANNOUNCEMENTS · TWITTER · TOS & SLA · Supported CI Services · What's a CI service? · Automated Testing

© 2026 Coveralls, Inc