nickg / nvc / 17346274433
93%
master: 93%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 98
Run time 1min
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Rst
coverage: 92.628% (+0.003%) from 92.625%
17346274433

push

github

nickg 
Check port widths match in mixed VHDL/Verilog elaboration

44 of 44 new or added lines in 4 files covered. (100.0%)

72773 of 78565 relevant lines covered (92.63%)

561944.67 hits per line

Jobs
ID Job ID Ran Files Coverage
1 17346274433.1 98
92.63
 GitHub Action Run
Source Files on build 17346274433