nickg / nvc / 17025294111
93%
master: 93%

LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran
Jobs 1
Files 98
Run time 1min
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Rst
coverage: 92.571% (+0.007%) from 92.564%
17025294111

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github

nickg 
Initial support for wide Verilog vectors

170 of 172 new or added lines in 9 files covered. (98.84%)

175 existing lines in 8 files now uncovered.

72233 of 78030 relevant lines covered (92.57%)

560908.33 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
94.35
 0.27% src/jit/jit-exits.c
1
97.28
 -0.03% src/jit/jit-irgen.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
98.55
 -0.12% src/jit/jit-optim.c
4
83.83
 -0.6% src/mir/mir-type.c
7
79.76
 1.84% src/vlog/vlog-util.c
19
43.48
 3.22% src/vpi/vpi-util.c
21
97.28
 -0.03% src/jit/jit-irgen.c
23
88.07
 0.38% src/vlog/vlog-number.c
48
83.13
 0.43% src/vpi/vpi-model.c
52
96.14
 -0.5% src/vlog/vlog-lower.c
Jobs
ID Job ID Ran Files Coverage
1 17025294111.1 98
92.57
 GitHub Action Run
Source Files on build 17025294111