16261973045
93%

Ran 14 Jul 2025 08:43AM UTC

Jobs 1

Files 99

Run time 1min

Badge

Committed 14 Jul 2025 08:30AM UTC coverage: 92.432% (+0.01%) from 92.422%

Build Type

push

github

Committed by

Commit Message

Parse Verilog escaped identifiers. Fixes #1237

Run Details

21 of 21 new or added lines in 3 files covered. (100.0%)

55 existing lines in 2 files now uncovered.

71673 of 77541 relevant lines covered (92.43%)

564667.31 hits per line

Lines	Coverage	∆	File
2	99.52	0.04%	src/vhdl/vhdl-predef.c
53	97.21	-0.02%	src/lower.c

ID	Job ID	Ran	Files	Coverage
1	16261973045.1	14 Jul 2025 08:43AM UTC	99	92.43	GitHub Action Run