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nickg / nvc / 16261687288
93%
master: 93%

Build:
Build:
LAST BUILD BRANCH: test
DEFAULT BRANCH: master
Ran 14 Jul 2025 08:30AM UTC
Jobs 1
Files 99
Run time 1min
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14 Jul 2025 08:16AM UTC coverage: 92.431% (+0.02%) from 92.411%
16261687288

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github

nickg
Parse Verilog escaped identifiers

21 of 21 new or added lines in 3 files covered. (100.0%)

55 existing lines in 2 files now uncovered.

71672 of 77541 relevant lines covered (92.43%)

566431.37 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
2
99.52
0.21% src/vhdl/vhdl-predef.c
53
97.21
-0.02% src/lower.c
Jobs
ID Job ID Ran Files Coverage
1 16261687288.1 14 Jul 2025 08:30AM UTC 99
92.43
GitHub Action Run
Source Files on build 16261687288
  • Tree
  • List 99
  • Changed 7
  • Source Changed 0
  • Coverage Changed 7
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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