nickg / nvc / 12564666753
93%

DEFAULT BRANCH: master
Ran
Jobs 1
Files 86
Run time 1min
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coverage: 92.117% (+0.06%) from 92.061%
12564666753

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github

nickg 
Correct error location after Verilog macro expansion

90 of 100 new or added lines in 5 files covered. (90.0%)

8 existing lines in 2 files now uncovered.

63807 of 69267 relevant lines covered (92.12%)

513073.61 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
96.2
 -0.12% src/vlog/vlog-pp.l
9
86.59
 -0.59% src/scan.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
90.16
 -0.18% src/thread.c
7
76.52
 -0.9% src/server.c
Jobs
ID Job ID Ran Files Coverage
1 12564666753.1 86
92.12
 GitHub Action Run
Source Files on build 12564666753