nickg / nvc / 12558119195
93%

DEFAULT BRANCH: master
Ran
Jobs 1
Files 86
Run time 1min
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coverage: 92.061% (+0.04%) from 92.023%
12558119195

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github

nickg 
Define Verilog preprocessor macros on command line

Based on code from @Blebowski in #1110

59 of 65 new or added lines in 7 files covered. (90.77%)

1 existing line in 1 file now uncovered.

63696 of 69189 relevant lines covered (92.06%)

512502.23 hits per line

New Missed Lines in Diff

Lines Coverage ∆ File
1
87.18
 0.26% src/scan.c
5
90.09
 -4.25% src/vpi/vpi-systf.c

Uncovered Existing Lines

Lines Coverage ∆ File
1
62.11
 1.83% src/nvc.c
Jobs
ID Job ID Ran Files Coverage
1 12558119195.1 86
92.06
 GitHub Action Run
Source Files on build 12558119195