nickg / nvc / 8040255646
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Jobs 1
Files 79
Run time 7s
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coverage: 91.66% (+0.007%) from 91.653%
8040255646

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github

nickg 
Add some basic support for Verilog module instantiation

52290 of 57048 relevant lines covered (91.66%)

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ID Job ID Ran Files Coverage
1 8040255646.1 0
91.66
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