cfelton / test_jpeg / 128
92%

DEFAULT BRANCH: master
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Jobs 4
Files 16
Run time 4min
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128

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cfelton 
Added missing ROM generation files

MyHDL ROM generation modules were used for the VHDL to Verilog
conversion.  These python modules generated the ROM tables used
in the design.

256 of 260 relevant lines covered (98.46%)

0.98 hits per line

Jobs
ID Job ID Ran Files Coverage
1 128.1 0
98.46
 Travis Job 128.1
2 128.2 0
98.46
 Travis Job 128.2
3 128.3 0
98.46
 Travis Job 128.3
4 128.4 0
98.46
 Travis Job 128.4
Source Files on build 128
Detailed source file information is not available for this build.