cfelton / test_jpeg / 128 / 1
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master: 92%

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coverage: 98.462%. Remained the same
128.1

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cfelton 
Added missing ROM generation files

MyHDL ROM generation modules were used for the VHDL to Verilog
conversion.  These python modules generated the ROM tables used
in the design.

64 of 65 relevant lines covered (98.46%)

0.98 hits per line

Source Files on job 128.1