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SystemRDL / systemrdl-compiler / 317 / 1
92%
main: 91%

Build:
Build:
LAST BUILD BRANCH: v1.32.1
DEFAULT BRANCH: main
Ran 09 Sep 2020 05:35AM UTC
Files 33
Run time 5s
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09 Sep 2020 05:30AM UTC coverage: 86.449% (+1.2%) from 85.266%
CIBW_SKIP="cp27-* *macosx_10_6*" SYSTEMRDL_REQUIRE_BINARY_BUILD=

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travis-ci

amykyta3
Implement Verilog Preprocessor. Reworked source reference insfrastructure. #41

1074 of 1388 branches covered (77.38%)

Branch coverage included in aggregate %.

4253 of 4774 relevant lines covered (89.09%)

0.89 hits per line

Source Files on job 317.1 (CIBW_SKIP="cp27-* *macosx_10_6*" SYSTEMRDL_REQUIRE_BINARY_BUILD=)
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  • Changed 3
  • Source Changed 1
  • Coverage Changed 3
Coverage ∆ File Lines Relevant Covered Missed Hits/Line Branch Hits Branch Misses
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