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sifive / duh-verilog / 30942e7a97b7b14ff061793263183e7d0afaf754 / 12
34%
master: 34%

Build:
DEFAULT BRANCH: master
Ran 15 Oct 2020 06:51PM UTC
Files 7
Run time 1s
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15 Oct 2020 06:49PM UTC coverage: 33.55% (-61.7%) from 95.294%
30942e7a97b7b14ff061793263183e7d0afaf754.12

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github

Aliaksei Chapyzhenka
proper verilog body generation

21 of 94 branches covered (22.34%)

Branch coverage included in aggregate %.

82 of 213 relevant lines covered (38.5%)

1.68 hits per line

Source Files on job 30942e7a97b7b14ff061793263183e7d0afaf754.12
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Coverage ∆ File Lines Relevant Covered Missed Hits/Line Branch Hits Branch Misses
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