SystemRDL / systemrdl-compiler / 323 / 1
94%
main: 91%

LAST BUILD BRANCH: v1.32.1
DEFAULT BRANCH: main
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Files 33
Run time 3s
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coverage: 91.815% (+0.6%) from 91.183%
CIBW_SKIP="cp27-* *macosx_10_6*" SYSTEMRDL_REQUIRE_BINARY_BUILD=

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amykyta3 
Implement Verilog Preprocessor. Reworked source reference insfrastructure. #41

Add type hints to some visitors.
Fixed error message bug
Verilog preprocessor unit tests

1171 of 1396 branches covered (83.88%)

Branch coverage included in aggregate %.

4505 of 4786 relevant lines covered (94.13%)

0.94 hits per line

Source Files on job 323.1 (CIBW_SKIP="cp27-* *macosx_10_6*" SYSTEMRDL_REQUIRE_BINARY_BUILD=)