4
92%
main: 91%

Ran 11 Sep 2020 04:48AM UTC

Files 33

Run time 3s

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Committed 11 Sep 2020 04:44AM UTC coverage: 91.81% (+5.4%) from 86.451%

Build Type

push

travis-ci

Committed by

Commit Message

Verilog preprocessor unit tests

Run Details

1171 of 1396 branches covered (83.88%)

Branch coverage included in aggregate %.

4501 of 4782 relevant lines covered (94.12%)

0.94 hits per line