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Ran 27 Feb 2020 04:15PM UTC

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Committed 27 Feb 2020 04:06PM UTC coverage: 73.31% (-9.9%) from 83.259%

Job # 399.1

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push

travis-ci-com

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web-flow

Commit Message

Visualizer for Pipelined CPU's (#124)

This visualizer was written in scala-swing and the goal is to display the modules used in the pipelined CPU design and their relative location between the pipeline registers. The visualization should reflect the value of I/O on the modules and update every cycle.

Features:

Designed with an MVC architecture based on a simplified circuit module and description of the pipelined CPU.
Loads LowFIRRTL through some AST parsing
Automatically places instances of modules to their correct pipeline register by running a DFS on the node graph to find modules connected to each pipeline register
Uses Treadle's peek() call to load values at ports.

You can run it with:

```
singularity exec library://jlowepower/default/dinocpu sbt "runMain dinocpu.visualize multiply.riscv"
```

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