jlpteaching / dinocpu / 399

72%

push

travis-ci-com

Visualizer for Pipelined CPU's (#124)

This visualizer was written in scala-swing and the goal is to display the modules used in the pipelined CPU design and their relative location between the pipeline registers. The visualization should reflect the value of I/O on the modules and update every cycle.

Features:

Designed with an MVC architecture based on a simplified circuit module and description of the pipelined CPU.
Loads LowFIRRTL through some AST parsing
Automatically places instances of modules to their correct pipeline register by running a DFS on the node graph to find modules connected to each pipeline register
Uses Treadle's peek() call to load values at ports.

You can run it with:

```
singularity exec library://jlowepower/default/dinocpu sbt "runMain dinocpu.visualize multiply.riscv"
```

274 of 274 new or added lines in 1 file covered. (100.0%)

1681 of 2293 relevant lines covered (73.31%)

0.73 hits per line