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master: 98%

Ran 04 Oct 2019 11:45AM UTC

Files 259

Run time 12s

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Committed 04 Oct 2019 11:39AM UTC coverage: 97.967%. Remained the same

Job # NAME="unix coverage build and tests"

Build Type

push

travis-ci

Committed by

dpgeorge

Commit Message

stm32/{adc,machine_adc}: Change ADC clock and sampling time for F0 MCUs.

STM32F0 has PCLK=48MHz and maximum ADC clock is 14MHz so use PCLK/4=12MHz
to stay within spec of the ADC peripheral.  In pyb.ADC set common sampling
time to approx 4uS for internal and external sources.  In machine.ADC
reduce sample time to approx 1uS for external source, leave internal at
maximum sampling time.

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