11521
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Ran 04 Oct 2019 11:45AM UTC

Jobs 1

Files 259

Run time 13s

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Build # 11521

Build Type

push

travis-ci

Committed by

dpgeorge

Commit Message

stm32/{adc,machine_adc}: Change ADC clock and sampling time for F0 MCUs.

STM32F0 has PCLK=48MHz and maximum ADC clock is 14MHz so use PCLK/4=12MHz
to stay within spec of the ADC peripheral.  In pyb.ADC set common sampling
time to approx 4uS for internal and external sources.  In machine.ADC
reduce sample time to approx 1uS for external source, leave internal at
maximum sampling time.

Run Details

18406 of 18788 relevant lines covered (97.97%)

345872.83 hits per line

Jobs

ID	Job ID	Ran	Files	Coverage
3	11521.3 (NAME="unix coverage build and tests")	04 Oct 2019 11:45AM UTC	0	97.97	Travis Job 11521.3

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