hriener / lorina / 166 / 1
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coverage: 87.161%. Remained the same
COMPILER=g++-7 COVERAGE=ON

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Merge pull request #19 from msoeken/msoeken/verilog-writer

More fine-grained control for I/O and wire names in Verilog writer

1188 of 1363 relevant lines covered (87.16%)

49.09 hits per line

Source Files on job 166.1 (COMPILER=g++-7 COVERAGE=ON)