hriener / lorina / 166
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Merge pull request #19 from msoeken/msoeken/verilog-writer

More fine-grained control for I/O and wire names in Verilog writer

1188 of 1363 relevant lines covered (87.16%)

49.09 hits per line

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ID Job ID Ran Files Coverage
1 166.1 (COMPILER=g++-7 COVERAGE=ON) 0
87.16
 Travis Job 166.1
Source Files on build 166
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