1
61%
master: 65%

Ran 30 May 2019 11:40PM UTC

Files 409

Run time 24s

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Committed 30 May 2019 11:28PM UTC coverage: 61.576%. Remained the same

Job # 833.1

Build Type

push

travis-ci

Committed by

BrunoDutertre

Commit Message

Bug fix: extend partial assignments from cadical to full assignments.

The bit-vector solver doesn't assign a value to a variable
x unless all the bits of x are set to either true or false by
the backend solver. If one bit of x is 'unknown' the bit-vector
solver sets the value of x to 'unknown', which may lead to an
incorrect model later on.

Run Details

60064 of 97545 relevant lines covered (61.58%)

1178603.54 hits per line

SRI-CSL / yices2 / 833 / 1
61%
master: 65%

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Source Files on job 833.1

SRI-CSL / yices2 / 833 / 1 61% master: 65%

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Markdown

Textile

RDoc

HTML

Rst

Source Files on job 833.1

SRI-CSL / yices2 / 833 / 1
61%
master: 65%

README BADGES
x