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SRI-CSL / yices2 / 833
61%
master: 65%

Build:
Build:
LAST BUILD BRANCH: 2.7.0
DEFAULT BRANCH: master
Ran 30 May 2019 11:40PM UTC
Jobs 1
Files 409
Run time 26s
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BrunoDutertre
Bug fix: extend partial assignments from cadical to full assignments.

The bit-vector solver doesn't assign a value to a variable
x unless all the bits of x are set to either true or false by
the backend solver. If one bit of x is 'unknown' the bit-vector
solver sets the value of x to 'unknown', which may lead to an
incorrect model later on.

60064 of 97545 relevant lines covered (61.58%)

1178603.54 hits per line

Jobs
ID Job ID Ran Files Coverage
1 833.1 30 May 2019 11:40PM UTC 0
61.58
Travis Job 833.1
Source Files on build 833
Detailed source file information is not available for this build.
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