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Ran 25 Jan 2019 05:07AM UTC

Files 43

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Committed 25 Jan 2019 04:55AM UTC coverage: 94.957% (+5.7%) from 89.254%

Job # 1503.1

Build Type

push

travis-ci-com

Committed by

alexcarsello

Commit Message

Interconnect Redesign (#147)

* work in progress to add config bus in

* style fix

* first pass of configuration

* add function to produce bitstream based on a connection

* fix a bug due to refactoring

* add top-level config_reg

* add thorough tests on interconnect policy. fixed related bugs

* refactor the dummy core

* add a simple config_reg test

* remove relative import

* add more config parameters

* remove duplicated wiring

* cb working. need to figure out a way to test sb

* sb circuit test working

* check in

* tile working

* add top-level interconnect class

* fix travis python

* switch back to python 3.6 style type annotation

* clean up

* fix refactor

* add back uniform test

* check in: bug fixes and start to test the interconnect

* interconnect working

* clean up and re-enable tests

* address issues and dead code in PR#147

Coverage Stats

1996 of 2102 relevant lines covered (94.96%)

0.95 hits per line

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StanfordAHA / garnet / 1503 / 1
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master: 98%

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