leonardt / silica / 162 / 1
57%
master: 74%

LAST BUILD BRANCH: jtag2
DEFAULT BRANCH: master
Ran
Files 33
Run time 2s
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Rst
coverage: 56.667%. First build
162.1

Pull #7

travis-ci

web-flow 
remove doctest
Pull Request #7: Init SSA based verilog synthesis

1241 of 2190 relevant lines covered (56.67%)

0.57 hits per line

Source Files on job 162.1