StanfordAHA / garnet / 523 / 1
96%
master: 98%

LAST BUILD BRANCH: simple_mapper
DEFAULT BRANCH: master
Ran
Files 20
Run time 1s
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Rst
coverage: 95.862% (-0.2%) from 96.028%
523.1

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travis-ci-com

alexcarsello 
Add assertion to check whether or not verilog sim completed w/o errors

417 of 435 relevant lines covered (95.86%)

0.96 hits per line

Source Files on job 523.1