2
70%
master: 57%

Ran 21 Oct 2016 04:24PM UTC

Files 175

Run time 9s

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Committed 21 Oct 2016 04:23PM UTC coverage: 70.348%. First build

Job # 457.2

Build Type

push

travis-ci

Committed by Christopher Felton

Commit Message

Remove phantom warnings in verilog conversion related to Xilinx device_clock_mgmt_prim (#54)

* Remove phantom warnings related to Xilinx device_clock_mgmt_prim

* Also removed phantom conversion warning about clockin not being read

Run Details

4695 of 6674 relevant lines covered (70.35%)

0.7 hits per line

cfelton / rhea / 457 / 2
70%
master: 57%

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Source Files on job 457.2

cfelton / rhea / 457 / 2 70% master: 57%

README BADGES x

Markdown

Textile

RDoc

HTML

Rst

Source Files on job 457.2

cfelton / rhea / 457 / 2
70%
master: 57%

README BADGES
x