nickg / nvc / 21265992745 / 1
93%
master: 93%

LAST BUILD BRANCH: random-initialization
DEFAULT BRANCH: master
Ran
Files 102
Run time 4s
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Rst
coverage: 92.616%. Remained the same
21265992745.1

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nickg 
Ensure unused vector bits are cleared after Verilog arithmetic

76285 of 82367 relevant lines covered (92.62%)

468238.41 hits per line

Source Files on job 21265992745.1