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cfelton / rhea / 456 / 1
57%
master: 57%

Build:
DEFAULT BRANCH: master
Ran 16 Aug 2016 11:21AM UTC
Files 175
Run time 8s
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16 Aug 2016 11:10AM UTC coverage: 70.348% (-0.04%) from 70.39%
456.1

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Remove phantom warnings in verilog conversion related to Xilinx device_clock_mgmt_prim (#54)

* Remove phantom warnings related to Xilinx device_clock_mgmt_prim

* Also removed phantom conversion warning about clockin not being read

4695 of 6674 relevant lines covered (70.35%)

0.7 hits per line

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