nickg / nvc / 17927677220 / 1
93%
master: 93%

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Run time 4s
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coverage: 92.658% (+0.02%) from 92.641%
17927677220.1

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nickg 
Add Verilog remainder and division operators

73865 of 79718 relevant lines covered (92.66%)

587821.11 hits per line

Source Files on job 17927677220.1