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nickg / nvc / 17517146210 / 1
93%
master: 93%

Build:
DEFAULT BRANCH: master
Ran 06 Sep 2025 05:11PM UTC
Files 99
Run time 3s
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06 Sep 2025 04:26PM UTC coverage: 92.654% (-0.004%) from 92.658%
17517146210.1

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Basic code generation for System Verilog enums

73315 of 79128 relevant lines covered (92.65%)

586503.95 hits per line

Source Files on job 17517146210.1
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  • Changed 10
  • Source Changed 0
  • Coverage Changed 10
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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