nickg / nvc / 17331952033 / 1
93%
master: 93%

LAST BUILD BRANCH: random-initialization
DEFAULT BRANCH: master
Ran
Files 98
Run time 4s
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Rst
coverage: 92.59% (+0.003%) from 92.587%
17331952033.1

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nickg 
Check Verilog variables are not connected to outputs

72607 of 78418 relevant lines covered (92.59%)

551172.17 hits per line

Source Files on job 17331952033.1