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cfelton / rhea / 418 / 2
57%
master: 57%

Build:
DEFAULT BRANCH: master
Ran 05 Aug 2016 05:03PM UTC
Files 174
Run time 9s
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05 Aug 2016 04:50PM UTC coverage: 70.33% (-0.02%) from 70.354%
418.2

Pull #40

travis-ci

web-flow
Added Clock.delay() to allow for easy delaying for a certain number of ticks of user clock signals
Pull Request #40: Fixed VHDL conversion via rhea.build.toolflow.convert, added Clock.ticks property, Clock.delay generator, fixed a typo + spacing

4672 of 6643 relevant lines covered (70.33%)

0.7 hits per line

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