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cfelton / rhea / 418
57%

Build:
DEFAULT BRANCH: master
Ran 05 Aug 2016 05:00PM UTC
Jobs 3
Files 522
Run time 2min
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418

Pull #40

travis-ci

web-flow
Added Clock.delay() to allow for easy delaying for a certain number of ticks of user clock signals
Pull Request #40: Fixed VHDL conversion via rhea.build.toolflow.convert, added Clock.ticks property, Clock.delay generator, fixed a typo + spacing

14018 of 19929 relevant lines covered (70.34%)

0.7 hits per line

Uncovered Existing Lines

Lines Coverage ∆ File
4
100.0
/home/travis/virtualenv/python3.4.2/lib/python3.4/site-packages/rhea/system/clock.py
4
100.0
/home/travis/virtualenv/python2.7.9/lib/python2.7/site-packages/rhea/system/clock.py
4
100.0
/home/travis/virtualenv/python3.5.2/lib/python3.5/site-packages/rhea/system/clock.py
Jobs
ID Job ID Ran Files Coverage
1 418.1 05 Aug 2016 05:00PM UTC 0
70.33
Travis Job 418.1
2 418.2 05 Aug 2016 05:03PM UTC 0
70.33
Travis Job 418.2
3 418.3 05 Aug 2016 05:00PM UTC 0
70.36
Travis Job 418.3
Source Files on build 418
Detailed source file information is not available for this build.
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  • Travis Build #418
  • Pull Request #40
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