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nickg / nvc / 16007625582 / 1
93%
master: 93%

Build:
DEFAULT BRANCH: master
Ran 01 Jul 2025 06:58PM UTC
Files 98
Run time 4s
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01 Jul 2025 06:13PM UTC coverage: 92.26% (+0.009%) from 92.251%
16007625582.1

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Map VHDL generics to Verilog parameters

70636 of 76562 relevant lines covered (92.26%)

569441.87 hits per line

Source Files on job 16007625582.1
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  • List 98
  • Changed 10
  • Source Changed 0
  • Coverage Changed 10
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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