Qiskit
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qiskit
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15687749088
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1
88%
main: 88%
main: 88%
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Ran
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Files
789
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Run time
34s
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coverage: 88.134% (-0.008%) from 88.142%
github
mergify[bot]Fix classical bit mapping in HLS pass (#14597) * Map classical bits from block to outer circuit Co-authored-by: Alexander Ivrii <alexi@il.ibm.com> * Add regression test * Add reno * Avoid allocating cargs Previously the cargs were being written to a Vec<usize> as an intermediate storage, however we are just returning them directly and don't need to allocate or change the types. This commit just works with the slice returned from the interner directly which both simplifies the code and should also be faster. --------- Co-authored-by: Alexander Ivrii <alexi@il.ibm.com> Co-authored-by: Matthew Treinish <mtreinish@kortar.org> (cherry picked from commit 9ec464af4)
72962 of 82785 relevant lines covered (88.13%)
346662.63 hits per line
