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PeterCDMcLean / BitLib / 15127475219 / 2
54%
master: 77%

Build:
Build:
LAST BUILD BRANCH: more_from_string_prototypes
DEFAULT BRANCH: master
Ran 20 May 2025 02:43AM UTC
Files 27
Run time 0s
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20 May 2025 02:28AM UTC coverage: 96.317% (+46.9%) from 49.385%
15127475219.2

Pull #12

github

web-flow
Merge f276d8ac2 into 9126838eb
Pull Request #12: Add a bounds type for SystemVerilog style slicing

1386 of 1439 relevant lines covered (96.32%)

15209734.29 hits per line

Source Files on job 15127475219.2
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  • List 27
  • Changed 26
  • Source Changed 0
  • Coverage Changed 26
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