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Ran 22 Jan 2025 11:55PM UTC

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Committed 22 Jan 2025 11:41PM UTC coverage: 64.101% (-0.1%) from 64.245%

Job # 12919139012.1

Build Type

push

github

Committed by

pcolberg

Commit Message

mem_tg: read NOC layout from TG feature register

Add High Bandwidth Memory (HBM) support to the memory traffic generator
(mem_tg) sample used to exercise and test available memory channels,
which currently supports DDR memory only. For DDR, each memory channel
accesses an independent memory bank, each starting from offset 0.

For HBM, each memory channel has access to the entire memory space and
must therefore access memory from different locations when reading or
writing on multiple channels simultaneously to avoid collisions.

For details on the HBM memory architecture, refer to the
Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide.

Link: https://cdrdv2-public.intel.com/780779/ug-768844-780779.pdf
Signed-off-by: Peter Colberg <peter.colberg@altera.com>

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15826 of 24689 relevant lines covered (64.1%)

8909.77 hits per line

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master: 64%

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