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OFS / opae-sdk / 12919139012
64%

Build:
DEFAULT BRANCH: master
Ran 22 Jan 2025 11:55PM UTC
Jobs 1
Files 146
Run time 1min
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22 Jan 2025 11:41PM UTC coverage: 64.101% (-0.1%) from 64.245%
12919139012

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pcolberg
mem_tg: read NOC layout from TG feature register

Add High Bandwidth Memory (HBM) support to the memory traffic generator
(mem_tg) sample used to exercise and test available memory channels,
which currently supports DDR memory only. For DDR, each memory channel
accesses an independent memory bank, each starting from offset 0.

For HBM, each memory channel has access to the entire memory space and
must therefore access memory from different locations when reading or
writing on multiple channels simultaneously to avoid collisions.

For details on the HBM memory architecture, refer to the
Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide.

Link: https://cdrdv2-public.intel.com/780779/ug-768844-780779.pdf
Signed-off-by: Peter Colberg <peter.colberg@altera.com>

0 of 38 new or added lines in 1 file covered. (0.0%)

88 existing lines in 2 files now uncovered.

15826 of 24689 relevant lines covered (64.1%)

8909.77 hits per line

New Missed Lines in Diff

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38
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0.0% samples/mem_tg/tg_test.h

Uncovered Existing Lines

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Jobs
ID Job ID Ran Files Coverage
1 12919139012.1 22 Jan 2025 11:55PM UTC 146
64.1
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Source Files on build 12919139012
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