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nickg / nvc / 10435290845 / 1
92%
master: 92%

Build:
DEFAULT BRANCH: master
Ran 17 Aug 2024 09:27PM UTC
Files 79
Run time 2s
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17 Aug 2024 08:49PM UTC coverage: 92.007% (-0.003%) from 92.01%
10435290845.1

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Code generation for Verilog primitive gates

58892 of 64008 relevant lines covered (92.01%)

656861.57 hits per line

Source Files on job 10435290845.1
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  • Changed 59
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  • Coverage Changed 6
Coverage ∆ File Lines Relevant Covered Missed Hits/Line
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