sifive / duh-verilog
34%

DEFAULT BRANCH: master
Repo Added
Files 7
Badge
Embed ▾
README BADGES
x

If you need to use a raster PNG badge, change the '.svg' to '.png' in the link

Markdown

Textile

RDoc

HTML

Rst

LAST BUILD ON BRANCH master
branch: master
CHANGE BRANCH
x

0d94ec6be580bf16583af47ad944d4c58f73d441

push

github

GitHub 
Merge pull request #4 from sifive/add-license-1

22 of 96 branches covered (22.92%)

Branch coverage included in aggregate %.

86 of 220 relevant lines covered (39.09%)

1.68 hits per line

Relevant lines Covered
220 RELEVANT LINES 86 COVERED LINES
1.68 HITS PER LINE
Source Files on master

Recent builds

Builds Branch Commit Type Ran Committer Via Coverage
0d94ec6b... master Merge pull request #4 from sifive/add-license-1 push GitHub github pending completion  
2305cf1b... master extra sapce instead of parameters push Aliaksei Chapyzhenka github pending completion  
603e2039... master :arrow_up: node 15 github actions push Aliaksei Chapyzhenka github pending completion  
741d8bee... master 0.3.0 push Aliaksei Chapyzhenka github pending completion  
30942e7a... master proper verilog body generation push Aliaksei Chapyzhenka github pending completion  
ba6c9068... master 0.2.0 push Aliaksei Chapyzhenka github pending completion  
427c0704... master minor lint clean push Aliaksei Chapyzhenka github pending completion  
8aa5d757... master test mix of ports with and without annotation push Aliaksei Chapyzhenka github pending completion  
8aa5d757... master test mix of ports with and without annotation push Aliaksei Chapyzhenka github pending completion  
cb0eb22a... master generate port list with busInterface annotations push Aliaksei Chapyzhenka github pending completion  
See All Builds (13)