sifive / duh-verilog / cb0eb22a68c6b06f96dcad16c946aef348dcbad8
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cb0eb22a68c6b06f96dcad16c946aef348dcbad8

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Aliaksei Chapyzhenka 
generate port list with busInterface annotations

19 of 22 branches covered (86.36%)

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52 of 53 relevant lines covered (98.11%)

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86.67
 -2.22% lib/vector-dim.js
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ID Job ID Ran Files Coverage
4 cb0eb22a68c6b06f96dcad16c946aef348dcbad8.4 4
94.67
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Source Files on build cb0eb22a68c6b06f96dcad16c946aef348dcbad8